1. Field
Exemplary embodiments of the present invention relate to a signal amplification circuit and method of reducing signal distortion in a device that an analog signal is amplified and converted into a digital signal.
2. Description of the Related Art
A signal amplification circuit is a circuit to amplify an input signal according to a gain. The reason to use the signal amplification circuits in the semiconductor device is in order to restore a signal distorted by various loadings or noises.
FIG. 1 is a configuration diagram illustrating a conventional signal amplification circuit.
Referring to FIG. 1, the signal amplification circuit includes a differential amplification unit 110 and inverting elements 120 and 130 configured to output different logic values depending on the levels of amplified signals OUT and OUTB of the differential amplification unit 110.
The differential amplification unit 110 is configured to amplify a voltage difference between an input signal IN and an input signal bar INB obtained by inverting the input signal IN, and generates an amplified signal OUT and an amplified signal bar OUTB. In a fully-differential input method that uses the input signals IN and INB, the input signals IN and INB have a symmetric waveform, and thus the amplified signals OUT and OUTB also have a symmetric waveform.
The first (1st) and the second (2nd) inverting elements 120 and 130 output a low-level signal when the level of the amplified signals OUT and OUTB are higher than a logic threshold, and a high-level signal when the level of the amplified signals OUT and OUTB are lower than the logic threshold. Output signals OUT1 and OUT2 respectively from the 1st and 2nd inverting elements 120 and 130 are the inverted versions of the input signals IN and INB.
FIG. 2 is a configuration diagram of the differential amplification unit 110.
Referring to FIG. 2, the differential amplification unit 110 may include two amplifiers 210 and 220. The 1st and 2nd amplifiers 210 and 220 have the same configuration, and include two NMOS transistors N1 and N2, two PMOS transistors P1 and P2, and a current source IS1. The two NMOS transistors N1 and N2 receive a power supply voltage VDD, and the sum of amounts of current flowing in the NMOS transistors N4 and N5 is constantly maintained by the current source IS1.
The 1st and 2nd amplifiers 210 and 220 respectively generate the amplified signals OUT and OUTB by amplifying a voltage difference between the input signals IN and INB.
When the voltage of a terminal A is higher than the voltage of a terminal B, a node C is pull-down driven by the NMOS transistor N1. Accordingly, the PMOS transistors P1 and P2 are turned on in response to the voltage of the node C, and an output node D is pull-up driven. On the other hand, when the voltage of the terminal A is higher than the voltage of the terminal B, the output node D is pull-down driven by the NMOS transistor N2.
The first amplifier 210 receives the input signals IN and INB through the terminals A and B, respectively, and outputs the amplified signal OUT. The 2nd amplifier 220 receives the input signal bar INB and the input signal IN through the terminals A and B, respectively, and outputs the amplified signal bar OUTB.
FIG. 3 is a configuration diagram of the inverting elements 120 and 130.
Referring to FIG. 3, the inverting element includes an NMOS transistor N3 and a PMOS transistor P3. When the voltage of an input node E is higher than the logic threshold, an output node F is pull-down driven by the NMOS transistor N3, and a low-level signal is outputted to the output node F. On the other hand, when the voltage of the input node E is lower than the logic threshold, the output node F is pull-up driven by the PMOS transistor P3 and a high-level signal is outputted to the output node F.
FIG. 4 is a waveform diagram illustrating concerns related to the conventional signal amplification circuit.
Due to the drivability limits of the transistors of the differential amplification unit 110 and the inverting elements 120 and 130, a signal may be delayed when passing through the differential amplification unit 110 and the inverting elements 120 and 130. The delay value may vary depending on the fabrication process of the amplification unit and the types of the transistors (NMOS or PMOS).
First waveform diagram 410 illustrates the waveforms of the amplified signals (OUT, OUTB), and the outputs (OUT1 and OUT2) of the 1st and 2nd inverting elements, illustrating the concerns raised by a delay difference according to the fabrication processes. It is supposed that there is only difference in delay among the fabrication processes, and that there are three fabrication processes, and that a time required for each transistor to completely drive a node is set to (1*unit time) for the first process, (3*unit time) for the second process, and (5*unit, time) for the third process.
In response to the transition of the input signal IN from a low level to a high level, the differential amplification unit 110 outputs a low level signal with the output node D of the 1st amplifier 210 pull-up driven by the PMOS transistor P2, and the output node F of the 1st inverting element 120 pull-down driven by the NMOS transistor N3. In the similar way, the differential amplification unit 110 outputs a high-level signal because the 2nd amplifier 210 and the 2nd inverting element 130 are driven in the different manner.
When the signal amplification circuit is fabricated by the first process, the amplifiers 210 and 220 require a driving time of (1*unit time), and the inverting elements 120 and 130 require a driving time of (1*unit time). Accordingly, (2*unit time) is required for completely driving the output of the 1st inverting element 120. Similarly, (6*unit time) is required in case of the second process, and (10*unit time) is required in case of the third process.
When the logic threshold LT of the inverting elements 120 and 130 is set to an intermediate value between a voltages of a low level and a high level, a time required for transition from input signals (IN, INB) to output signals (OUT1, OUT2) corresponds to (1.5*unit time) in case of the first process, (4.5*unit time) in case of the second process, and (7.5*unit time) in case of the third process. Difference between the times required in cases of the first and third processes, corresponds to (6*unit time), which means that the performance of the signal amplification circuit becomes sensitive to the process.
Second waveform diagram 420 illustrates the waveforms of the amplified signals OUT and OUTB, the output signals OUT1 and OUT2, illustrating a concern raised by a delay difference based on a drivability difference between NMOS and PMOS transistors. It is supposed that there is only the delay difference based on the drivability difference between the NMOS and PMOS transistors, and that a time required for each transistor to completely drive a node is set to (2*unit time) for the NMOS transistor, and (4*unit time for the PMOS transistor.
In response to the transition of the input signal IN from a low level to a high level, the differential amplification unit 110 outputs a low-level signal with the output node D of the 1st amplifier 210 pull-up driven by the PMOS transistor P2, and the output node F of the 1st inverting element 120 pull-down driven by the NMOS transistor N3. In the similar way, the differential amplification unit 110 outputs a high-level signal because the 2nd amplifier 210 and the 2nd inverting element 130 are driven in the opposite manner.
Therefore, the 1st amplifier 210 requires a driving time of (4*unit time), and the 1st inverting element 120 requires a driving time of (2*unit time). Accordingly, (5*unit time) is required for completely driving the output of the 1st inverting element 120.
Similarly, the 2nd amplifier 220 requires a driving time of (2*unit time), and the 2nd inverting element 130 requires a driving time of (4*unit time). Accordingly, (4*unit time) is required for completely driving the output of the 2nd inverting element 130.
Since the input signals IN and INB are differential signals, the outputs OUT1 and OUT2 of the inverting elements 120 and 130 have the inversion relation. According to the above-described configuration, however, the time point between when the logic value of the output OUT1 changes and when the logic value of the output OUT2 changes differs from each other.
In addition, the relation between the outputs OUT1 and OUT2 of the 1st and 2nd inverting elements may be distorted because of path difference of input signals IN and INB to the 1st and 2nd amplifiers 210 and 220.
Due to the above-described concerns a duty ratio of output signal outputted from the signal amplification circuit may be distorted, and the relation between two output signals outputted from the signal amplification circuit may be distorted.